74AUP2G79GS,115
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2010 |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.35mm |
| Base Part Number | 74AUP2G79 |
| Function | Standard |
| Output Type | Non-Inverted |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Clock Frequency | 309MHz |
| Propagation Delay | 25.6 ns |
| Turn On Delay Time | 2 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.35mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74AUP2G79GS,115 Overview
The flip flop is packaged in 8-XFDFN. It is contained within the Tape & Reel (TR)package. T flip flop uses Non-Invertedas its output configuration. The trigger configured with it uses Positive Edge. This electronic part is mounted in the way of Surface Mount. Powered by a 0.8V~3.6Vvolt supply, it operates as follows. In this case, the operating temperature is -40°C~125°C TA. The type of this D latch is D-Type. JK flip flop is a part of the 74AUPseries of FPGAs. In order for it to function properly, its output frequency should not exceed 309MHz. A total of 2elements are present in it. T flip flop consumes 500nA quiescent energy. The number of terminations is 8. D latch belongs to the 74AUP2G79 family. Power is supplied from a voltage of 1.1V volts. The input capacitance of this JK flip flopis 0.6pF farads. AUP/ULP/Vis the family of this D flip flop. In this case, the electronic component is mounted in the way of Surface Mount. A total of 8pins are provided on this board. Its clock edge trigger type is Positive Edge. 3.6Vis the maximum supply voltage (Vsup).
74AUP2G79GS,115 Features
Tape & Reel (TR) package
74AUP series
8 pins
74AUP2G79GS,115 Applications
There are a lot of Nexperia USA Inc. 74AUP2G79GS,115 Flip Flops applications.
- Clock pulse
- Divide a clock signal by 2 or 4
- 2 – Bit synchronous counter
- EMI reduction circuitry
- Latch
- Balanced Propagation Delays
- Buffered Clock
- Supports Live Insertion
- Digital electronics systems
- Control circuits
