74AUP2G80GN,115
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2010 |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.3mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP2G80 |
| Function | Standard |
| Output Type | Inverted |
| Number of Elements | 2 |
| Polarity | Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Clock Frequency | 309MHz |
| Propagation Delay | 27.2 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2.2 ns |
| Family | AUP/ULP/V |
| Current - Output High, Low | 4mA 4mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.35mm |
| RoHS Status | ROHS3 Compliant |
74AUP2G80GN,115 Overview
The flip flop is packaged in a case of 8-XFDFN. The Tape & Reel (TR)package contains it. There is a Invertedoutput configured with it. It is configured with the trigger Positive Edge. Surface Mountis in the way of this electric part. A 0.8V~3.6Vsupply voltage is required for it to operate. It is operating at a temperature of -40°C~125°C TA. The type of this D latch is D-Type. FPGAs belonging to the 74AUPseries contain this type of chip. It should not exceed 309MHzin terms of its output frequency. The element count is 2 . It has been determined that there have been 8 terminations. This D latch belongs to the family of 74AUP2G80. An input voltage of 1.1Vpowers the D latch. Input capacitance of this device is 0.6pF farads. Devices in the AUP/ULP/Vfamily are electronic devices. There is an electronic component mounted in the way of Surface Mount. Basically, it is designed with a set of 8 pins. This device has the clock edge trigger type of Positive Edge. As soon as Vsup reaches 3.6V, the maximum supply voltage is reached. Despite external influences, it consumes 500nAof quiescent current.
74AUP2G80GN,115 Features
Tape & Reel (TR) package
74AUP series
8 pins
74AUP2G80GN,115 Applications
There are a lot of Nexperia USA Inc. 74AUP2G80GN,115 Flip Flops applications.
- Circuit Design
- Power down protection
- Memory
- High Performance Logic for test systems
- Guaranteed simultaneous switching noise level
- Balanced 24 mA output drivers
- CMOS Process
- ESD protection
- Digital electronics systems
- Supports Live Insertion
