74F109SJ
| Parameters | |
|---|---|
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Clock Frequency | 125MHz |
| Family | F/FAST |
| Current - Quiescent (Iq) | 17mA |
| Current - Output High, Low | 1mA 20mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 8ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| fmax-Min | 90 MHz |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tube |
| Series | 74F |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | MATTE TIN |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
74F109SJ Overview
The flip flop is packaged in 16-SOIC (0.209, 5.30mm Width). The package Tubecontains it. T flip flop is configured with an output of Differential. In the configuration of the trigger, Positive Edgeis used. There is an electric part mounted in the way of Surface Mount. The JK flip flop operates at 4.5V~5.5Vvolts. In the operating environment, the temperature is 0°C~70°C TA. This logic flip flop is classified as type JK Type. It belongs to the 74Fseries of FPGAs. A frequency of 125MHzshould not be exceeded by its output. The list contains 2 elements. There is a consumption of 17mAof quiescent energy. In 16terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. A voltage of 5V provides power to the D latch. This D flip flop belongs to the family of F/FAST. As soon as Vsup reaches 5.5V, the maximum supply voltage is reached. A normal operating voltage (Vsup) should remain above 4.5V.
74F109SJ Features
Tube package
74F series
74F109SJ Applications
There are a lot of Rochester Electronics, LLC 74F109SJ Flip Flops applications.
- Frequency Dividers
- Buffer registers
- Bus hold
- ESD performance
- Storage registers
- Shift registers
- Divide a clock signal by 2 or 4
- Load Control
- Parallel data storage
- Single Up Count-Control Line
