74F377SJ
| Parameters | |
|---|---|
| Series | 74F |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Additional Feature | WITH HOLD MODE |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Clock Frequency | 130MHz |
| Family | F/FAST |
| Current - Quiescent (Iq) | 48mA |
| Current - Output High, Low | 1mA 20mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 7ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Propagation Delay (tpd) | 9 ns |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tube |
74F377SJ Overview
20-SOIC (0.209, 5.30mm Width)is the packaging method. There is an embedded version in the package Tube. As configured, the output uses Non-Inverted. There is a trigger configured with Positive Edge. There is an electronic component mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 4.5V~5.5V volts. 0°C~70°C TAis the operating temperature. D-Typedescribes this flip flop. The FPGA belongs to the 74F series. You should not exceed 130MHzin the output frequency of the device. In total, it contains 1 elements. It consumes 48mA of quiescent 20terminations have occurred. A voltage of 5V is used to power it. An electronic device belonging to the family F/FASTcan be found here. It reaches the maximum supply voltage (Vsup) at 5.5V. Normally, the supply voltage (Vsup) should be above 4.5V. In addition, you can refer to the additinal WITH HOLD MODE of the D latch.
74F377SJ Features
Tube package
74F series
74F377SJ Applications
There are a lot of Rochester Electronics, LLC 74F377SJ Flip Flops applications.
- Synchronous counter
- 2 – Bit synchronous counter
- ESD performance
- Reduced system switching noise
- Communications
- Individual Asynchronous Resets
- Data Synchronizers
- Shift Registers
- Supports Live Insertion
- ESCC
