74F533SJ
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C |
| Packaging | Tube |
| Series | 74F |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Terminal Finish | MATTE TIN |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Number of Functions | 1 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Pin Count | 20 |
| JESD-30 Code | R-PDSO-G20 |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State |
| Circuit | 8:8 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Number of Bits | 8 |
| Family | F/FAST |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 3mA 24mA |
| Logic Type | D-Type Transparent Latch |
| Output Polarity | INVERTED |
| Independent Circuits | 1 |
| Delay Time - Propagation | 6.7ns |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74F533SJ Overview
In the 20-SOIC (0.209, 5.30mm Width) package, it can be found as an embedded module. Tube is the way it is packaged. In this configuration, the output is set to Tri-State. D-Type Transparent Latch is the logic type of this electrical device. This electronic part is mounted in the way of Surface Mount. The supply voltage of the device is 4.5V~5.5V. There is a temperature of 0°C~70°C at which the system operates. An FPGA in this series belongs to the 74F family. Electronic parts with 8 bits are designed for this application. The device consists of 20 terminations that are designed to be used in conjunction with it. With a supply voltage of 5V, it operates. With 20 pins, it is equipped. It is part of the family of electronic devices called F/FAST. There are 2 ports, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. It reaches a maximum supply voltage (Vsup) of 5.5V. It is recommended to have a higher supply voltage (Vsup) than 4.5V.
74F533SJ Features
20-SOIC (0.209, 5.30mm Width) package
74F series
8 Bits
20 pin count
74F533SJ Applications
There are a lot of Rochester Electronics, LLC 74F533SJ Latches applications.
- Relay replacement
- Four-bit storage with output enable
- Decade counting
- Parallel Output
- Digital bus buffer
- Shift left register
- Buffer Storage
- Shift register
- Automotive ADAS
- Display driver
