Parameters |
Mounting Type |
Through Hole |
Package / Case |
20-DIP (0.300, 7.62mm) |
Supplier Device Package |
20-PDIP |
Operating Temperature |
0°C~70°C TA |
Packaging |
Tube |
Series |
74F |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Type |
D-Type |
Voltage - Supply |
4.5V~5.5V |
Base Part Number |
74F534 |
Function |
Standard |
Output Type |
Tri-State, Inverted |
Number of Elements |
1 |
Polarity |
Inverting |
Clock Frequency |
100MHz |
Current - Quiescent (Iq) |
86mA |
Current - Output High, Low |
3mA 24mA |
Number of Bits per Element |
8 |
Max Propagation Delay @ V, Max CL |
8.5ns @ 5V, 50pF |
Trigger Type |
Positive Edge |
Lead Free |
Lead Free |
74F534PC Overview
20-DIP (0.300, 7.62mm)is the packaging method. It is contained within the Tubepackage. Currently, the output is configured to use Tri-State, Inverted. There is a trigger configured with Positive Edge. This electronic part is mounted in the way of Through Hole. A 4.5V~5.5Vsupply voltage is required for it to operate. It is operating at 0°C~70°C TA. The type of this D latch is D-Type. This type of FPGA is a part of the 74F series. Its output frequency should not exceed 100MHz. In total, there are 1 elements. There is a consumption of 86mAof quiescent energy. The 74F534 family contains this object.
74F534PC Features
Tube package
74F series
74F534PC Applications
There are a lot of ON Semiconductor 74F534PC Flip Flops applications.
- ESD performance
- Matched Rise and Fall
- Frequency Divider circuits
- Communications
- EMI reduction circuitry
- Divide a clock signal by 2 or 4
- Circuit Design
- Asynchronous counter
- Shift registers
- Data transfer