74HC107D,652
| Parameters | |
|---|---|
| Family | HC/UH |
| Current - Quiescent (Iq) | 4μA |
| Current - Output High, Low | 5.2mA 5.2mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 27ns @ 6V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 48 ns |
| fmax-Min | 60 MHz |
| Length | 8.65mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 14-SOIC (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Number of Pins | 14 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 2013 |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74HC107 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Load Capacitance | 50pF |
| Output Current | 25mA |
| Clock Frequency | 85MHz |
74HC107D,652 Overview
The flip flop is packaged in 14-SOIC (0.154, 3.90mm Width). D flip flop is embedded in the Tube package. It is configured with Differentialas an output. It is configured with a trigger that uses a value of Negative Edge. In this case, the electronic component is mounted in the way of Surface Mount. Powered by a 2V~6Vvolt supply, it operates as follows. Temperature is set to -40°C~125°C TA. This electronic flip flop is of type JK Type. JK flip flop is a part of the 74HCseries of FPGAs. In order for it to function properly, its output frequency should not exceed 85MHz. In total, there are 2 elements. This process consumes 4μA quiescents. In 14terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. Members of the 74HC107family make up this object. A voltage of 5V provides power to the D latch. The input capacitance of this JK flip flopis 3.5pF farads. It is a member of the HC/UHfamily of D flip flop. This board has 14 pins. It reaches 6Vwhen the supply voltage is maximal (Vsup). If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 2V. With a current output of 25mA , it offers maximum design flexibility.
74HC107D,652 Features
Tube package
74HC series
14 pins
74HC107D,652 Applications
There are a lot of Nexperia USA Inc. 74HC107D,652 Flip Flops applications.
- Frequency division
- Communications
- Clock pulse
- Guaranteed simultaneous switching noise level
- Instrumentation
- Shift Registers
- Modulo – n – counter
- Set-reset capability
- ESD performance
- Power down protection
