Parameters |
Factory Lead Time |
1 Week |
Mounting Type |
Surface Mount |
Package / Case |
16-SSOP (0.209, 5.30mm Width) |
Surface Mount |
YES |
Operating Temperature |
-40°C~125°C TA |
Packaging |
Tape & Reel (TR) |
Published |
2010 |
Series |
74HC |
JESD-609 Code |
e4 |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
16 |
Type |
JK Type |
Terminal Finish |
Nickel/Palladium/Gold (Ni/Pd/Au) |
Technology |
CMOS |
Voltage - Supply |
2V~6V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
260 |
Supply Voltage |
4.5V |
Terminal Pitch |
0.65mm |
Reach Compliance Code |
compliant |
Time@Peak Reflow Temperature-Max (s) |
30 |
Base Part Number |
74HC112 |
Function |
Set(Preset) and Reset |
Qualification Status |
Not Qualified |
Output Type |
Differential |
Number of Elements |
2 |
Supply Voltage-Max (Vsup) |
6V |
Supply Voltage-Min (Vsup) |
2V |
Load Capacitance |
50pF |
Clock Frequency |
71MHz |
Family |
HC/UH |
Current - Quiescent (Iq) |
4μA |
Current - Output High, Low |
5.2mA 5.2mA |
Output Polarity |
COMPLEMENTARY |
Number of Bits per Element |
1 |
Max Propagation Delay @ V, Max CL |
30ns @ 6V, 50pF |
Trigger Type |
Negative Edge |
Input Capacitance |
3.5pF |
Width |
5.3mm |
RoHS Status |
RoHS Compliant |
74HC112DB,118 Overview
The flip flop is packaged in a case of 16-SSOP (0.209, 5.30mm Width). It is contained within the Tape & Reel (TR)package. T flip flop uses Differentialas its output configuration. The trigger it is configured with uses Negative Edge. Surface Mountis occupied by this electronic component. The JK flip flop operates at 2V~6Vvolts. The operating temperature is -40°C~125°C TA. The type of this D latch is JK Type. It belongs to the 74HCseries of FPGAs. A frequency of 71MHzshould be the maximum output frequency. The list contains 2 elements. It consumes 4μA of quiescent It has been determined that there have been 16 terminations. The object belongs to the 74HC112 family. The power supply voltage is 4.5V. A 3.5pFfarad input capacitance is provided by this T flip flop. It is a member of the HC/UHfamily of D flip flop. As soon as 6Vis reached, Vsup reaches its maximum value. For normal operation, the supply voltage (Vsup) should be kept above 2V.
74HC112DB,118 Features
Tape & Reel (TR) package
74HC series
74HC112DB,118 Applications
There are a lot of Nexperia USA Inc. 74HC112DB,118 Flip Flops applications.
- Set-reset capability
- Single Up Count-Control Line
- High Performance Logic for test systems
- Balanced 24 mA output drivers
- Data Synchronizers
- Instrumentation
- Balanced Propagation Delays
- Frequency Divider circuits
- Bounce elimination switch
- Divide a clock signal by 2 or 4