74HC112PW,118
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 16-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 1998 |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 4.5V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74HC112 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Load Capacitance | 50pF |
| Clock Frequency | 71MHz |
| Family | HC/UH |
| Current - Quiescent (Iq) | 4μA |
| Current - Output High, Low | 5.2mA 5.2mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 30ns @ 6V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 3.5pF |
| Length | 5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74HC112PW,118 Overview
16-TSSOP (0.173, 4.40mm Width)is the way it is packaged. As part of the package Tape & Reel (TR), it is embedded. There is a Differentialoutput configured with it. Negative Edgeis the trigger it is configured with. In this case, the electronic component is mounted in the way of Surface Mount. A voltage of 2V~6Vis required for its operation. It is operating at a temperature of -40°C~125°C TA. Logic flip flops of this type are classified as JK Type. JK flip flop belongs to the 74HCseries of FPGAs. You should not exceed 71MHzin its output frequency. A total of 2 elements are present. This process consumes 4μA quiescents. Currently, there are 16 terminations. D latch belongs to the 74HC112 family. It is powered by a voltage of 4.5V . A JK flip flop with a 3.5pFfarad input capacitance is used here. Electronic devices of this type belong to the HC/UHfamily. It reaches 6Vwhen the supply voltage is maximal (Vsup). Normally, the supply voltage (Vsup) should be kept above 2V.
74HC112PW,118 Features
Tape & Reel (TR) package
74HC series
74HC112PW,118 Applications
There are a lot of Nexperia USA Inc. 74HC112PW,118 Flip Flops applications.
- ESCC
- Asynchronous counter
- QML qualified product
- Memory
- Test & Measurement
- Memory
- Balanced 24 mA output drivers
- Functionally equivalent to the MC10/100EL29
- Shift Registers
- Storage Registers
