74HC377PW,112
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 20 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Additional Feature | WITH HOLD MODE |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Supply Voltage | 5V |
| Terminal Pitch | 0.65mm |
| Base Part Number | 74HC377 |
| Function | Standard |
| Output Type | Non-Inverted |
| Operating Supply Voltage | 5V |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Bits | 8 |
| Clock Frequency | 83MHz |
| Propagation Delay | 240 ns |
| Quiescent Current | 8μA |
| Turn On Delay Time | 13 ns |
| Family | HC/UH |
| Logic Function | D-Type, Flip-Flop |
| Current - Output High, Low | 5.2mA 5.2mA |
| Max Propagation Delay @ V, Max CL | 27ns @ 6V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Number of Input Lines | 8 |
| fmax-Min | 24 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Length | 6.5mm |
| Width | 4.4mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
74HC377PW,112 Overview
20-TSSOP (0.173, 4.40mm Width)is the packaging method. As part of the package Tube, it is embedded. T flip flop is configured with an output of Non-Inverted. JK flip flop uses Positive Edgeas the trigger. Surface Mountmounts this electrical part. A supply voltage of 2V~6V is required for operation. A temperature of -40°C~125°C TAis considered to be the operating temperature. This D latch has the type D-Type. The 74HCseries comprises this type of FPGA. A frequency of 83MHzshould be the maximum output frequency. D latch consists of 1 elements. A total of 20terminations have been recorded. JK flip flop belongs to 74HC377 family. A voltage of 5V is used as the power supply for this D latch. Its input capacitance is 3.5pF farads. An electronic device belonging to the family HC/UHcan be found here. In this case, the electronic component is mounted in the way of Surface Mount. There are 20pins on it. A Positive Edgeclock edge trigger is used in this device. There are 8bits in its design. There is a 6Vmaximum supply voltage (Vsup). For normal operation, the supply voltage (Vsup) should be above 2V. For high efficiency, the supply voltage should be set to 5V. A total of 8input lines have been provided. It consumes a total of 8μA quiescent current at any given time. Additionally, there are WITH HOLD MODE on the electronic flip flop that can be referred to.
74HC377PW,112 Features
Tube package
74HC series
20 pins
8 Bits
74HC377PW,112 Applications
There are a lot of Nexperia USA Inc. 74HC377PW,112 Flip Flops applications.
- Count Modes
- Test & Measurement
- Frequency division
- 2 – Bit synchronous counter
- ATE
- CMOS Process
- Digital electronics systems
- Dynamic threshold performance
- High Performance Logic for test systems
- Latch-up performance
