74HC73DB,118
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-SSOP (0.209, 5.30mm Width) |
| Number of Pins | 14 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | JK Type |
| Additional Feature | MASTER SLAVE OPERATION |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74HC73 |
| Function | Reset |
| Output Type | Differential |
| Operating Supply Voltage | 5V |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Clock Frequency | 83MHz |
| Propagation Delay | 16 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 15 ns |
| Family | HC/UH |
| Logic Function | Flip-Flop, JK-Type |
| Current - Output High, Low | 5.2mA 5.2mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 27ns @ 6V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 3.5pF |
| Clock Edge Trigger Type | Negative Edge |
| Width | 5.3mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
74HC73DB,118 Overview
As a result, it is packaged as 14-SSOP (0.209, 5.30mm Width). You can find it in the Tape & Reel (TR)package. It is configured with Differentialas an output. In the configuration of the trigger, Negative Edgeis used. There is an electronic component mounted in the way of Surface Mount. A supply voltage of 2V~6V is required for operation. A temperature of -40°C~125°C TAis considered to be the operating temperature. The type of this D latch is JK Type. JK flip flop belongs to the 74HCseries of FPGAs. In order for it to function properly, its output frequency should not exceed 83MHz. A total of 14terminations have been recorded. This D latch belongs to the family of 74HC73. It is powered from a supply voltage of 5V. This JK flip flop has a 3.5pFfarad input capacitance. It belongs to the family of electronic devices known as HC/UH. In this case, the electronic component is mounted in the way of Surface Mount. Basically, it is designed with a set of 14 pins. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Negative Edge. It reaches the maximum supply voltage (Vsup) at 6V. For normal operation, the supply voltage (Vsup) should be above 2V. Despite its superior flexibility, it relies on 2 circuits to achieve it. If high efficiency is desired, the supply voltage should be kept at 5V. As a result, it consumes 4μA of quiescent current without being affected by external factors. In addition, you can refer to the additinal MASTER SLAVE OPERATION of the D latch.
74HC73DB,118 Features
Tape & Reel (TR) package
74HC series
14 pins
74HC73DB,118 Applications
There are a lot of Nexperia USA Inc. 74HC73DB,118 Flip Flops applications.
- Single Down Count-Control Line
- CMOS Process
- EMI reduction circuitry
- High Performance Logic for test systems
- Computing
- Synchronous counter
- Frequency division
- Individual Asynchronous Resets
- Frequency Divider circuits
- Load Control
