74LCX112MX
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 week ago) |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 16 |
| Weight | 143mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2005 |
| Series | 74LCX |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | CMOS |
| Voltage - Supply | 2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 2.5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LCX112 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2V |
| Clock Frequency | 150MHz |
| Propagation Delay | 8 ns |
| Quiescent Current | 10μA |
| Turn On Delay Time | 7 ns |
| Family | LVC/LCX/Z |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 7.5ns @ 3.3V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 7pF |
| Number of Input Lines | 5 |
| Clock Edge Trigger Type | Negative Edge |
| Length | 9.9mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74LCX112MX Overview
The flip flop is packaged in a case of 16-SOIC (0.154, 3.90mm Width). Package Tape & Reel (TR)embeds it. Differentialis the output configured for it. The trigger it is configured with uses Negative Edge. Surface Mountis positioned in the way of this electronic part. A voltage of 2V~3.6Vis required for its operation. -40°C~85°C TAis the operating temperature. This D latch has the type JK Type. It is a type of FPGA belonging to the 74LCX series. In order for it to function properly, its output frequency should not exceed 150MHz. In total, it contains 2 elements. In 16terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74LCX112 family contains this object. It is powered by a voltage of 2.5V . The input capacitance of this JK flip flopis 7pF farads. This D flip flop belongs to the family of LVC/LCX/Z. A part of the electronic system is mounted in the way of Surface Mount. This board is designed with 16pins on it. In this device, the clock edge trigger type is Negative Edge. There is a base part number FF/Latchesfor the RS flip flops. Vsup reaches its maximum value at 3.6V. The supply voltage (Vsup) should be kept above 2V for normal operation. As a result of its reliability, this D flip flop is ideally suited for TAPE AND REEL. The D latch operates on 3.3V volts. A total of 5input lines have been provided. It consumes a total of 10μA quiescent current at any given time.
74LCX112MX Features
Tape & Reel (TR) package
74LCX series
16 pins
3.3V power supplies
74LCX112MX Applications
There are a lot of ON Semiconductor 74LCX112MX Flip Flops applications.
- Common Clocks
- Functionally equivalent to the MC10/100EL29
- Differential Individual
- Matched Rise and Fall
- Individual Asynchronous Resets
- Safety Clamp
- Computing
- Counters
- Buffer registers
- Dynamic threshold performance
