74LCX112SJ
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LCX |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Function | Set(Preset) and Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2V |
| Clock Frequency | 150MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 7.5ns @ 3.3V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 7pF |
| Propagation Delay (tpd) | 9 ns |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LCX112SJ Overview
The flip flop is packaged in a case of 16-SOIC (0.209, 5.30mm Width). As part of the package Tube, it is embedded. There is a Differentialoutput configured with it. This trigger is configured to use Negative Edge. It is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 2V~3.6V volts. In this case, the operating temperature is -40°C~85°C TA. JK Typeis the type of this D latch. In terms of FPGAs, it belongs to the 74LCX series. Its output frequency should not exceed 150MHz Hz. In total, it contains 2 elements. It consumes 10μA of quiescent Currently, there are 16 terminations. The D flip flop is powered by a voltage of 2.5V . Its input capacitance is 7pFfarads. Electronic devices of this type belong to the LVC/LCX/Zfamily. The maximal supply voltage (Vsup) reaches 3.6V. The supply voltage (Vsup) should be kept above 2V for normal operation.
74LCX112SJ Features
Tube package
74LCX series
74LCX112SJ Applications
There are a lot of Rochester Electronics, LLC 74LCX112SJ Flip Flops applications.
- High Performance Logic for test systems
- Pattern generators
- Common Clocks
- QML qualified product
- Single Up Count-Control Line
- Consumer
- Single Down Count-Control Line
- Event Detectors
- Memory
- Frequency division
