74LCX821WM
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 24-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LCX |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| JESD-30 Code | R-PDSO-G24 |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Ports | 2 |
| Clock Frequency | 150MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 7ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 7pF |
| Propagation Delay (tpd) | 8.4 ns |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
74LCX821WM Overview
In the form of 24-SOIC (0.295, 7.50mm Width), it has been packaged. It is included in the package Tube. As configured, the output uses Tri-State, Non-Inverted. It is configured with a trigger that uses Positive Edge. Surface Mountis positioned in the way of this electronic part. With a supply voltage of 2V~3.6V volts, it operates. Currently, the operating temperature is -40°C~85°C TA. D-Typeis the type of this D latch. In this case, it is a type of FPGA belonging to the 74LCX series. A frequency of 150MHzshould be the maximum output frequency. The list contains 1 elements. As a result, it consumes 10μA quiescent current and is not affected by external forces. It has been determined that there have been 24 terminations. Power is provided by a 2.5V supply. This JK flip flop has a 7pFfarad input capacitance. In this case, the D flip flop belongs to the LVC/LCX/Zfamily. There is a 3.6Vmaximum supply voltage (Vsup). It is imperative that the supply voltage (Vsup) is maintained above 2Vin order to ensure normal operation. The flip flop contains 2ports.
74LCX821WM Features
Tube package
74LCX series
74LCX821WM Applications
There are a lot of Rochester Electronics, LLC 74LCX821WM Flip Flops applications.
- Functionally equivalent to the MC10/100EL29
- Individual Asynchronous Resets
- ESCC
- Latch
- Parallel data storage
- High Performance Logic for test systems
- Safety Clamp
- Differential Individual
- Data transfer
- Convert a momentary switch to a toggle switch
