74LV174D,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Supplier Device Package | 16-SO |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LV |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 1V~5.5V |
| Function | Master Reset |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Clock Frequency | 100MHz |
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 6 |
| Max Propagation Delay @ V, Max CL | 21ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| RoHS Status | ROHS3 Compliant |
74LV174D,112 Overview
It is embeded in 16-SOIC (0.154, 3.90mm Width) case. D flip flop is embedded in the Tube package. As configured, the output uses Non-Inverted. This trigger is configured to use Positive Edge. Surface Mountis positioned in the way of this electronic part. It operates with a supply voltage of 1V~5.5V. In this case, the operating temperature is -40°C~125°C TA. It is an electronic flip flop with the type D-Type. This type of FPGA is a part of the 74LV series. There should be no greater frequency than 100MHzon its output. The element count is 1 . There is 160μA quiescent consumption. A JK flip flop with a 3.5pFfarad input capacitance is used here.
74LV174D,112 Features
Tube package
74LV series
74LV174D,112 Applications
There are a lot of Rochester Electronics, LLC 74LV174D,112 Flip Flops applications.
- Guaranteed simultaneous switching noise level
- CMOS Process
- Shift registers
- Patented noise
- Power down protection
- Data transfer
- Synchronous counter
- Cold spare funcion
- Frequency division
- Divide a clock signal by 2 or 4
