74LV174D,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 1998 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV174 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Clock Frequency | 100MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 12mA 12mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 6 |
| Max Propagation Delay @ V, Max CL | 21ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| fmax-Min | 20 MHz |
| Max Frequency@Nom-Sup | 20000000Hz |
| Length | 9.9mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
74LV174D,112 Overview
The package is in the form of 16-SOIC (0.154, 3.90mm Width). It is contained within the Tubepackage. There is a Non-Invertedoutput configured with it. The trigger it is configured with uses Positive Edge. It is mounted in the way of Surface Mount. A supply voltage of 1V~5.5V is required for operation. Currently, the operating temperature is -40°C~125°C TA. This electronic flip flop is of type D-Type. JK flip flop is a part of the 74LVseries of FPGAs. Its output frequency should not exceed 100MHz Hz. In total, it contains 1 elements. Despite external influences, it consumes 160μAof quiescent current. It has been determined that there have been 16 terminations. This D latch belongs to the family of 74LV174. The D flip flop is powered by a voltage of 3.3V . This JK flip flop has a 3.5pFfarad input capacitance. This D flip flop belongs to the family of LV/LV-A/LVX/H. There is a base part number FF/Latchesfor the RS flip flops. There is a 5.5Vmaximum supply voltage (Vsup). For normal operation, the supply voltage (Vsup) should be above 1V. In order for the device to operate, it requires 3.3V power supplies.
74LV174D,112 Features
Tube package
74LV series
3.3V power supplies
74LV174D,112 Applications
There are a lot of NXP USA Inc. 74LV174D,112 Flip Flops applications.
- Modulo – n – counter
- Buffered Clock
- Buffer registers
- Clock pulse
- Convert a momentary switch to a toggle switch
- Matched Rise and Fall
- Latch
- Test & Measurement
- Differential Individual
- Event Detectors
