74LV174D,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 1998 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV174 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Clock Frequency | 100MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 12mA 12mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 6 |
| Max Propagation Delay @ V, Max CL | 21ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| fmax-Min | 20 MHz |
| Max Frequency@Nom-Sup | 20000000Hz |
| Length | 9.9mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
74LV174D,118 Overview
In the form of 16-SOIC (0.154, 3.90mm Width), it has been packaged. D flip flop is embedded in the Tape & Reel (TR) package. In the configuration, Non-Invertedis used as the output. It is configured with the trigger Positive Edge. Surface Mountmounts this electrical part. The JK flip flop operates at a voltage of 1V~5.5V. Temperature is set to -40°C~125°C TA. It is an electronic flip flop with the type D-Type. The FPGA belongs to the 74LV series. You should not exceed 100MHzin its output frequency. In total, it contains 1 elements. During its operation, it consumes 160μA quiescent energy. There are 16 terminations,JK flip flop belongs to 74LV174 family. A voltage of 3.3V is used as the power supply for this D latch. This T flip flop has a capacitance of 3.5pF farads at the input. In terms of electronic devices, this device belongs to the LV/LV-A/LVX/Hfamily of devices. There is a FF/Latchesbase part number assigned to the RS flip flops. As soon as 5.5Vis reached, Vsup reaches its maximum value. For normal operation, the supply voltage (Vsup) should be kept above 1V. This D flip flop is well suited for TAPE AND REEL based on its reliable performance. In order for the device to operate, it requires 3.3V power supplies.
74LV174D,118 Features
Tape & Reel (TR) package
74LV series
3.3V power supplies
74LV174D,118 Applications
There are a lot of NXP USA Inc. 74LV174D,118 Flip Flops applications.
- Supports Live Insertion
- High Performance Logic for test systems
- Pattern generators
- Buffer registers
- Shift registers
- Data transfer
- Consumer
- QML qualified product
- ESD performance
- Frequency division
