74LV273DB,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SSOP (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 1998 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV273 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Clock Frequency | 100MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 12mA 12mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 19ns @ 5V, 50pF |
| Prop. Delay@Nom-Sup | 24 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 24 ns |
| fmax-Min | 20 MHz |
| Max Frequency@Nom-Sup | 20000000Hz |
| Height Seated (Max) | 2mm |
| Length | 7.2mm |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LV273DB,118 Overview
It is packaged in the way of 20-SSOP (0.209, 5.30mm Width). There is an embedded version in the package Tape & Reel (TR). T flip flop uses Non-Invertedas the output. The trigger it is configured with uses Positive Edge. Surface Mountis in the way of this electric part. The JK flip flop operates with an input voltage of 1V~5.5V volts. Temperature is set to -40°C~125°C TA. Logic flip flops of this type are classified as D-Type. It is a type of FPGA belonging to the 74LV series. Its output frequency should not exceed 100MHz. In total, there are 1 elements. As a result, it consumes 160μA of quiescent current without being affected by external factors. 20terminations have occurred. D latch belongs to the 74LV273 family. It is powered from a supply voltage of 3.3V. JK flip flop input capacitance is 3.5pF farads. LV/LV-A/LVX/His the family of this D flip flop. It is part of the FF/Latchesbase part number family. Vsup reaches its maximum value at 5.5V. For normal operation, the supply voltage (Vsup) should be kept above 1V. There are 3.3V power supplies attached to it.
74LV273DB,118 Features
Tape & Reel (TR) package
74LV series
3.3V power supplies
74LV273DB,118 Applications
There are a lot of NXP USA Inc. 74LV273DB,118 Flip Flops applications.
- Storage registers
- ESD protection
- Bounce elimination switch
- Consumer
- Synchronous counter
- Registers
- CMOS Process
- Test & Measurement
- Balanced 24 mA output drivers
- High Performance Logic for test systems
