74LV273PW,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Supplier Device Package | 20-TSSOP |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LV |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 1V~5.5V |
| Function | Master Reset |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Clock Frequency | 100MHz |
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 19ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| RoHS Status | ROHS3 Compliant |
74LV273PW,112 Overview
20-TSSOP (0.173, 4.40mm Width)is the packaging method. It is contained within the Tubepackage. T flip flop uses Non-Invertedas the output. There is a trigger configured with Positive Edge. Surface Mountmounts this electrical part. The JK flip flop operates with an input voltage of 1V~5.5V volts. -40°C~125°C TAis the operating temperature. The type of this D latch is D-Type. This type of FPGA is a part of the 74LV series. In order for it to function properly, its output frequency should not exceed 100MHz. The element count is 1 . There is a consumption of 160μAof quiescent energy. Input capacitance of this device is 3.5pF farads.
74LV273PW,112 Features
Tube package
74LV series
74LV273PW,112 Applications
There are a lot of Rochester Electronics, LLC 74LV273PW,112 Flip Flops applications.
- Common Clocks
- Power down protection
- Shift Registers
- Counters
- Frequency Divider circuits
- Bounce elimination switch
- Data storage
- Digital electronics systems
- Data transfer
- Load Control
