74LV273PW,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Supplier Device Package | 20-TSSOP |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LV |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 1V~5.5V |
| Function | Master Reset |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Clock Frequency | 100MHz |
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 16ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| RoHS Status | ROHS3 Compliant |
74LV273PW,118 Overview
The flip flop is packaged in 20-TSSOP (0.173, 4.40mm Width). It is included in the package Tape & Reel (TR). In the configuration, Non-Invertedis used as the output. Positive Edgeis the trigger it is configured with. This electronic part is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 1V~5.5V volts. A temperature of -40°C~125°C TAis considered to be the operating temperature. D-Typeis the type of this D latch. In this case, it is a type of FPGA belonging to the 74LV series. In order for it to function properly, its output frequency should not exceed 100MHz. The list contains 1 elements. As a result, it consumes 160μA quiescent current and is not affected by external forces. This JK flip flop has a 3.5pFfarad input capacitance.
74LV273PW,118 Features
Tape & Reel (TR) package
74LV series
74LV273PW,118 Applications
There are a lot of Rochester Electronics, LLC 74LV273PW,118 Flip Flops applications.
- Clock pulse
- Instrumentation
- Safety Clamp
- Bus hold
- Synchronous counter
- Individual Asynchronous Resets
- Data transfer
- Patented noise
- Supports Live Insertion
- 2 – Bit synchronous counter
