74LV374DB,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SSOP (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 2009 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV374 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Clock Frequency | 77MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 160μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 16mA 16mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 19ns @ 5V, 50pF |
| Prop. Delay@Nom-Sup | 29 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 49 ns |
| Max Frequency@Nom-Sup | 20000000Hz |
| Height Seated (Max) | 2mm |
| Length | 7.2mm |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LV374DB,112 Overview
It is embeded in 20-SSOP (0.209, 5.30mm Width) case. You can find it in the Tubepackage. T flip flop is configured with an output of Tri-State, Non-Inverted. The trigger configured with it uses Positive Edge. The electronic part is mounted in the way of Surface Mount. It operates with a supply voltage of 1V~5.5V. It is at -40°C~125°C TAdegrees Celsius that the system is operating. This electronic flip flop is of type D-Type. It belongs to the 74LVseries of FPGAs. There should be no greater frequency than 77MHzon its output. D latch consists of 1 elements. As a result, it consumes 160μA quiescent current. Terminations are 20. Members of the 74LV374family make up this object. A voltage of 3.3V is used to power it. The input capacitance of this JK flip flopis 3.5pF farads. LV/LV-A/LVX/His the family of this D flip flop. The RS flip flops belongs to FF/Latches base part number. Vsup reaches 5.5V, the maximal supply voltage. For normal operation, the supply voltage (Vsup) should be above 1V. There are 3.3V power supplies attached to it. A total of 2ports are embedded in the D flip flop.
74LV374DB,112 Features
Tube package
74LV series
3.3V power supplies
74LV374DB,112 Applications
There are a lot of NXP USA Inc. 74LV374DB,112 Flip Flops applications.
- Data transfer
- ESCC
- Memory
- Load Control
- ATE
- QML qualified product
- Single Down Count-Control Line
- Set-reset capability
- Counters
- Parallel data storage
