74LV374N,112
| Parameters | |
|---|---|
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LV |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Type | D-Type |
| Voltage - Supply | 1V~5.5V |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Clock Frequency | 70MHz |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 16mA 16mA |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 20ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Through Hole |
| Package / Case | 20-DIP (0.300, 7.62mm) |
| Supplier Device Package | 20-DIP |
74LV374N,112 Overview
The flip flop is packaged in 20-DIP (0.300, 7.62mm). You can find it in the Tubepackage. T flip flop uses Tri-State, Non-Invertedas its output configuration. It is configured with a trigger that uses a value of Positive Edge. In this case, the electronic component is mounted in the way of Through Hole. A voltage of 1V~5.5Vis used as the supply voltage. It is operating at -40°C~125°C TA. The type of this D latch is D-Type. JK flip flop is a part of the 74LVseries of FPGAs. You should not exceed 70MHzin the output frequency of the device. D latch consists of 1 elements. It consumes 20μA of quiescent Its input capacitance is 3.5pFfarads.
74LV374N,112 Features
Tube package
74LV series
74LV374N,112 Applications
There are a lot of Rochester Electronics, LLC 74LV374N,112 Flip Flops applications.
- ATE
- Shift registers
- CMOS Process
- Cold spare funcion
- ESD protection
- Patented noise
- Supports Live Insertion
- Frequency Divider circuits
- Differential Individual
- Functionally equivalent to the MC10/100EL29
