74LV377N,112
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 20-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 1998 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Additional Feature | WITH HOLD MODE |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1V~3.6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 2.54mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV377 |
| JESD-30 Code | R-PDIP-T20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Clock Frequency | 70MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 6mA 6mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 30ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 36 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 36 ns |
| fmax-Min | 20 MHz |
| Max Frequency@Nom-Sup | 20000000Hz |
| Height Seated (Max) | 4.2mm |
| Length | 26.73mm |
| Width | 7.62mm |
| RoHS Status | ROHS3 Compliant |
74LV377N,112 Overview
The item is packaged in 20-DIP (0.300, 7.62mm)cases. D flip flop is embedded in the Tube package. It is configured with Non-Invertedas an output. Positive Edgeis the trigger it is configured with. Through Holeis positioned in the way of this electronic part. It operates with a supply voltage of 1V~3.6V. It is operating at -40°C~125°C TA. This logic flip flop is classified as type D-Type. JK flip flop belongs to the 74LVseries of FPGAs. This D flip flop should not have a frequency greater than 70MHz. A total of 1elements are contained within it. There is a consumption of 20μAof quiescent energy. The number of terminations is 20. You can search similar parts based on 74LV377. A voltage of 3.3V is used to power it. The input capacitance of this JK flip flopis 3.5pF farads. Electronic devices of this type belong to the LV/LV-A/LVX/Hfamily. The part is included in FF/Latches. As soon as Vsup reaches 5.5V, the maximum supply voltage is reached. For normal operation, the supply voltage (Vsup) should be kept above 1V. The power supply is 3.3V. In addition, you can refer to the additinal WITH HOLD MODE of the D latch.
74LV377N,112 Features
Tube package
74LV series
3.3V power supplies
74LV377N,112 Applications
There are a lot of NXP USA Inc. 74LV377N,112 Flip Flops applications.
- Memory
- Memory
- Shift Registers
- Load Control
- Clock pulse
- Supports Live Insertion
- Data Synchronizers
- Synchronous counter
- Modulo – n – counter
- Single Up Count-Control Line
