74LV377PW,118
| Parameters | |
|---|---|
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 6mA 6mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 30ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 36 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 36 ns |
| fmax-Min | 20 MHz |
| Max Frequency@Nom-Sup | 20000000Hz |
| Length | 6.5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 1998 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Additional Feature | WITH HOLD MODE |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV377 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Clock Frequency | 70MHz |
| Family | LV/LV-A/LVX/H |
74LV377PW,118 Overview
The flip flop is packaged in a case of 20-TSSOP (0.173, 4.40mm Width). As part of the package Tape & Reel (TR), it is embedded. This output is configured with Non-Inverted. This trigger is configured to use Positive Edge. There is an electric part mounted in the way of Surface Mount. With a supply voltage of 1V~3.6V volts, it operates. Currently, the operating temperature is -40°C~125°C TA. This logic flip flop is classified as type D-Type. The FPGA belongs to the 74LV series. This D flip flop should not have a frequency greater than 70MHz. A total of 1elements are contained within it. It consumes 160μA of quiescent current without being affected by external factors. Currently, there are 20 terminations. The 74LV377 family contains this object. A voltage of 3.3V is used as the power supply for this D latch. Its input capacitance is 3.5pF farads. LV/LV-A/LVX/His the family of this D flip flop. This device is part of the FF/Latchesbase part number family. Vsup reaches its maximum value at 5.5V. It is imperative that the supply voltage (Vsup) is maintained above 1Vin order to ensure normal operation. The system runs on a power supply of 3.3V watts. Furthermore, it has WITH HOLD MODEas a characteristic.
74LV377PW,118 Features
Tape & Reel (TR) package
74LV series
3.3V power supplies
74LV377PW,118 Applications
There are a lot of NXP USA Inc. 74LV377PW,118 Flip Flops applications.
- Computers
- Registers
- Event Detectors
- Individual Asynchronous Resets
- Functionally equivalent to the MC10/100EL29
- Instrumentation
- Data transfer
- Safety Clamp
- Latch-up performance
- Frequency Dividers
