74LV573D,112
| Parameters | |
|---|---|
| Series | 74LV |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Additional Feature | BROADSIDE VERSION OF 373 |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Number of Functions | 1 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV573 |
| Pin Count | 20 |
| JESD-30 Code | R-PDSO-G20 |
| Qualification Status | Not Qualified |
| Output Type | Tri-State |
| Circuit | 8:8 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Number of Bits | 8 |
| Family | LV/LV-A/LVX/H |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 16mA 16mA |
| Logic Type | D-Type Transparent Latch |
| Output Polarity | TRUE |
| Max I(ol) | 0.008 A |
| Prop. Delay@Nom-Sup | 29 ns |
| Independent Circuits | 1 |
| Delay Time - Propagation | 24ns |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C |
| Packaging | Tube |
| Published | 2009 |
74LV573D,112 Overview
In the 20-SOIC (0.295, 7.50mm Width) package, it can be found as an embedded module. Packaged in the way of Tube. In its configuration, Tri-State is used as the output. This electrical device has a logic type of D-Type Transparent Latch. According to Surface Mount, this electronic part is mounted. A 1V~5.5V supply voltage is required to operate it. A temperature of -40°C~125°C is set as the operating temperature. The 74LV series of FPGAs is the one this FPGA belongs to. It is designed with 8 bits. This device is designed with 20 terminations. It is a member of the 74LV573 family. In order to operate it, the supply voltage must be 3.3V. It has 20 pins that makes it easy to use. There is a device in this electronic family called LV/LV-A/LVX/H. This device has 2 ports. The part is in the FF/Latches subcategory. When Vsup reaches 5.5V, the maximal supply voltage is reached. The device is powered by 3.3V power supplies. A voltage greater than 1V must be supplied as a power supply (Vsup). It is also characterized by BROADSIDE VERSION OF 373.
74LV573D,112 Features
20-SOIC (0.295, 7.50mm Width) package
74LV series
8 Bits
74LV573 family
20 pin count
3.3V power supplies
74LV573D,112 Applications
There are a lot of NXP USA Inc. 74LV573D,112 Latches applications.
- Communication systems
- Audio and video switching
- Shift right register
- Multi-line decoders
- Automotive HEV/EV Powertrain
- Buffer/Storage Registers
- Synchronous frequency dividers
- Control circuits
- Parallel Output
- A/D converters
