74LV574N,112
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 20-DIP (0.300, 7.62mm) |
| Supplier Device Package | 20-DIP |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LV |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Type | D-Type |
| Voltage - Supply | 1V~5.5V |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Clock Frequency | 70MHz |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 16mA 16mA |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 17ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| RoHS Status | ROHS3 Compliant |
74LV574N,112 Overview
In the form of 20-DIP (0.300, 7.62mm), it has been packaged. There is an embedded version in the package Tube. T flip flop uses Tri-State, Non-Invertedas the output. It is configured with the trigger Positive Edge. Through Holemounts this electrical part. A supply voltage of 1V~5.5V is required for operation. Temperature is set to -40°C~125°C TA. This electronic flip flop is of type D-Type. FPGAs belonging to the 74LVseries contain this type of chip. It should not exceed 70MHzin terms of its output frequency. In total, there are 1 elements. As a result, it consumes 20μA quiescent current and is not affected by external forces. JK flip flop input capacitance is 3.5pF farads.
74LV574N,112 Features
Tube package
74LV series
74LV574N,112 Applications
There are a lot of Rochester Electronics, LLC 74LV574N,112 Flip Flops applications.
- Divide a clock signal by 2 or 4
- EMI reduction circuitry
- Computers
- Frequency Dividers
- ATE
- Shift Registers
- Guaranteed simultaneous switching noise level
- Control circuits
- Balanced 24 mA output drivers
- ESD protection
