74LV574PW,112
| Parameters | |
|---|---|
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LV |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 1V~5.5V |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Clock Frequency | 70MHz |
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 16mA 16mA |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 17ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Supplier Device Package | 20-TSSOP |
74LV574PW,112 Overview
The package is in the form of 20-TSSOP (0.173, 4.40mm Width). There is an embedded version in the package Tube. T flip flop uses Tri-State, Non-Invertedas its output configuration. JK flip flop uses Positive Edgeas the trigger. Surface Mountmounts this electrical part. The supply voltage is set to 1V~5.5V. The operating temperature is -40°C~125°C TA. Logic flip flops of this type are classified as D-Type. JK flip flop belongs to the 74LVseries of FPGAs. You should not exceed 70MHzin its output frequency. The element count is 1 . As a result, it consumes 160μA quiescent current. Its input capacitance is 3.5pF farads.
74LV574PW,112 Features
Tube package
74LV series
74LV574PW,112 Applications
There are a lot of Rochester Electronics, LLC 74LV574PW,112 Flip Flops applications.
- Bus hold
- Shift Registers
- Matched Rise and Fall
- Parallel data storage
- Asynchronous counter
- Data transfer
- ESCC
- Divide a clock signal by 2 or 4
- 2 – Bit synchronous counter
- Clock pulse
