74LV74D,112
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 14 |
| Supplier Device Package | 14-SO |
| Weight | 4.535924g |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 2013 |
| Series | 74LV |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Max Operating Temperature | 125°C |
| Min Operating Temperature | -40°C |
| Voltage - Supply | 1V~5.5V |
| Frequency | 110MHz |
| Base Part Number | 74LV74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Operating Supply Voltage | 3.3V |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Number of Circuits | 2 |
| Max Supply Voltage | 5.5V |
| Min Supply Voltage | 1V |
| Output Current | 12mA |
| Number of Bits | 2 |
| Clock Frequency | 110MHz |
| Propagation Delay | 17 ns |
| Quiescent Current | 20μA |
| Turn On Delay Time | 11 ns |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 17ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| High Level Output Current | -12mA |
| Input Capacitance | 3.5pF |
| Low Level Output Current | 12mA |
| Number of Input Lines | 1 |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Height | 6.35mm |
| Length | 6.35mm |
| Width | 6.35mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
74LV74D,112 Overview
It is embeded in 14-SOIC (0.154, 3.90mm Width) case. D flip flop is included in the Tubepackage. Currently, the output is configured to use Differential. This trigger uses the value Positive Edge. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates with an input voltage of 1V~5.5V volts. It is at -40°C~125°C TAdegrees Celsius that the system is operating. There is D-Type type of electronic flip flop associated with this device. FPGAs belonging to the 74LVseries contain this type of chip. In order for it to function properly, its output frequency should not exceed 110MHz. In total, there are 2 elements. T flip flop consumes 20μA quiescent energy. D latch belongs to the 74LV74 family. The input capacitance of this T flip flop is 3.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. It is mounted by the way of Surface Mount. It is designed with 14 pins. This device exhibits a clock edge trigger type of Positive Edge. An electronic part with 2bits has been designed. The superior flexibility is achieved through the use of 2 circuits. In order to ensure high efficiency, the supply voltage should remain at 3.3V. The output current of 12mA makes it feature maximum design flexibility. In order to operate, the chip has 1 output lines. There are 1 input Lines, which consist of an electronic circuit connected between the ac mains and the rectifier input stage of the switching power supply. There is 20μA quiescent current consumption by it. The high level output current is set to -12mA. A 12mAvalue is set for low-level output current. There should be a temperature below 125°Cduring operation. It should be higher than -40°Cwhen the system is operating. Normally, it operates with a voltage of 1VV as its minimum supply voltage. A maximum voltage of 5.5V can be provided by it. This can be achieved at a frequency of 110MHz.
74LV74D,112 Features
Tube package
74LV series
14 pins
2 Bits
74LV74D,112 Applications
There are a lot of Nexperia USA Inc. 74LV74D,112 Flip Flops applications.
- QML qualified product
- 2 – Bit synchronous counter
- Common Clocks
- Event Detectors
- ESD performance
- Automotive
- Differential Individual
- Synchronous counter
- Frequency Divider circuits
- Convert a momentary switch to a toggle switch
