74LV74D,118
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 14 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2013 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Operating Supply Voltage | 3.3V |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 1V |
| Number of Circuits | 2 |
| Clock Frequency | 110MHz |
| Propagation Delay | 11 ns |
| Quiescent Current | 80μA |
| Turn On Delay Time | 58 ns |
| Family | LV/LV-A/LVX/H |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 17ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Number of Output Lines | 1 |
| fmax-Min | 56 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Length | 8.65mm |
| Width | 3.9mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74LV74D,118 Overview
The flip flop is packaged in a case of 14-SOIC (0.154, 3.90mm Width). You can find it in the Tape & Reel (TR)package. T flip flop is configured with an output of Differential. This trigger uses the value Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. The supply voltage is set to 1V~5.5V. -40°C~125°C TAis the operating temperature. D-Typedescribes this flip flop. JK flip flop belongs to the 74LVseries of FPGAs. It should not exceed 110MHzin its output frequency. It consumes 20μA of quiescent current without being affected by external factors. In 14terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74LV74 family contains this object. It is powered by a voltage of 3.3V . There is 3.5pF input capacitance for this T flip flop. An electronic device belonging to the family LV/LV-A/LVX/Hcan be found here. There is an electronic component mounted in the way of Surface Mount. With its 14pins, it is designed to work with most electronic flip flops. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. As soon as 5.5Vis reached, Vsup reaches its maximum value. Normally, the supply voltage (Vsup) should be above 1V. Due to its superior flexibility, it uses 2 circuits. It is recommended that the supply voltage be kept at 3.3Vto maximize efficiency. It has 1 output lines to operate. 80μAquiescent current consumed.
74LV74D,118 Features
Tape & Reel (TR) package
74LV series
14 pins
74LV74D,118 Applications
There are a lot of Nexperia USA Inc. 74LV74D,118 Flip Flops applications.
- Functionally equivalent to the MC10/100EL29
- Count Modes
- Power down protection
- Data storage
- QML qualified product
- Memory
- Frequency Dividers
- Balanced 24 mA output drivers
- Digital electronics systems
- 2 – Bit synchronous counter
