74LV74N,112
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 14-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 2013 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | BULK PACK |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV74 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Clock Frequency | 110MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 12mA 12mA |
| Output Polarity | COMPLEMENTARY |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 17ns @ 5V, 50pF |
| Prop. Delay@Nom-Sup | 33 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 33 ns |
| fmax-Min | 48 MHz |
| Max Frequency@Nom-Sup | 48000000Hz |
| RoHS Status | ROHS3 Compliant |
74LV74N,112 Overview
The item is packaged in 14-DIP (0.300, 7.62mm)cases. As part of the package Tube, it is embedded. There is a Differentialoutput configured with it. This trigger is configured to use Positive Edge. This electronic part is mounted in the way of Through Hole. A supply voltage of 1V~5.5V is required for operation. It is at -40°C~125°C TAdegrees Celsius that the system is operating. This electronic flip flop is of type D-Type. It is a type of FPGA belonging to the 74LV series. Its output frequency should not exceed 110MHz. D latch consists of 2 elements. This process consumes 20μA quiescents. Currently, there are 14 terminations. If you search by 74LV74, you will find similar parts. Power is provided by a 3.3V supply. Its input capacitance is 3.5pF farads. In this case, the D flip flop belongs to the LV/LV-A/LVX/Hfamily. There is a FF/Latchesbase part number assigned to the RS flip flops. The maximal supply voltage (Vsup) reaches 5.5V. It is imperative that the supply voltage (Vsup) is maintained above 1Vin order to ensure normal operation. In view of its reliability, this D flip flop is a good fit for BULK PACK. In order for the device to operate, it requires 3.3V power supplies.
74LV74N,112 Features
Tube package
74LV series
3.3V power supplies
74LV74N,112 Applications
There are a lot of NXP USA Inc. 74LV74N,112 Flip Flops applications.
- Balanced 24 mA output drivers
- Divide a clock signal by 2 or 4
- Reduced system switching noise
- Automotive
- Cold spare funcion
- Buffered Clock
- Latch-up performance
- 2 – Bit synchronous counter
- Modulo – n – counter
- Count Modes
