74LV74PW,112
| Parameters | |
|---|---|
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Number of Output Lines | 1 |
| fmax-Min | 56 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Length | 5mm |
| Width | 4.4mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 14 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 2012 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Operating Supply Voltage | 3.3V |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 1V |
| Number of Circuits | 2 |
| Clock Frequency | 110MHz |
| Propagation Delay | 11 ns |
| Quiescent Current | 80μA |
| Turn On Delay Time | 58 ns |
| Family | LV/LV-A/LVX/H |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 17ns @ 5V, 50pF |
74LV74PW,112 Overview
The package is in the form of 14-TSSOP (0.173, 4.40mm Width). It is contained within the Tubepackage. T flip flop uses Differentialas the output. It is configured with a trigger that uses Positive Edge. Surface Mountmounts this electrical part. The supply voltage is set to 1V~5.5V. A temperature of -40°C~125°C TAis considered to be the operating temperature. It is an electronic flip flop with the type D-Type. JK flip flop is a part of the 74LVseries of FPGAs. A frequency of 110MHzshould be the maximum output frequency. T flip flop consumes 20μA quiescent energy. There are 14 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. Members of the 74LV74family make up this object. The power source is powered by 3.3V. JK flip flop input capacitance is 3.5pF farads. The electronic device belongs to the LV/LV-A/LVX/Hfamily. In this case, the electronic component is mounted in the way of Surface Mount. Basically, it is designed with a set of 14 pins. There is a clock edge trigger type of Positive Edgeon this device. In this case, the maximum supply voltage (Vsup) reaches 5.5V. The supply voltage (Vsup) should be maintained above 1V for normal operation. In order to achieve its superior flexibility, 2 circuits are used. The supply voltage should be maintained at 3.3V for high efficiency. It has 1 output lines to operate. There is a consumption of 80μAof quiescent current from it.
74LV74PW,112 Features
Tube package
74LV series
14 pins
74LV74PW,112 Applications
There are a lot of Nexperia USA Inc. 74LV74PW,112 Flip Flops applications.
- Communications
- Bus hold
- Test & Measurement
- Differential Individual
- Dynamic threshold performance
- Instrumentation
- Power down protection
- Safety Clamp
- Event Detectors
- Cold spare funcion
