74LV74PW,118
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 14 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2013 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Operating Supply Voltage | 3.3V |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 1V |
| Number of Circuits | 2 |
| Output Current | 25mA |
| Clock Frequency | 110MHz |
| Propagation Delay | 58 ns |
| Quiescent Current | 80μA |
| Turn On Delay Time | 58 ns |
| Family | LV/LV-A/LVX/H |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 17ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Number of Output Lines | 1 |
| fmax-Min | 56 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Length | 5mm |
| Width | 4.4mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74LV74PW,118 Overview
It is packaged in the way of 14-TSSOP (0.173, 4.40mm Width). The package Tape & Reel (TR)contains it. As configured, the output uses Differential. In the configuration of the trigger, Positive Edgeis used. The electronic part is mounted in the way of Surface Mount. A supply voltage of 1V~5.5V is required for operation. A temperature of -40°C~125°C TAis considered to be the operating temperature. This D latch has the type D-Type. The FPGA belongs to the 74LV series. It should not exceed 110MHzin terms of its output frequency. Currently, there are 14 terminations. Members of the 74LV74family make up this object. The power supply voltage is 3.3V. There is 3.5pF input capacitance for this T flip flop. A device of this type belongs to the family of LV/LV-A/LVX/H. This electronic part is mounted in the way of Surface Mount. There are 14pins on it. This device exhibits a clock edge trigger type of Positive Edge. Vsup reaches its maximum value at 5.5V. The supply voltage (Vsup) should be kept above 1V for normal operation. Its superior flexibility is attributed to its use of 2 circuits. In order to achieve high efficiency, the supply voltage should be maintained at 3.3V. The output current of 25mA makes it feature maximum design flexibility. There are 1 output lines in this JK flip flop. There is a consumption of 80μAof quiescent current from it.
74LV74PW,118 Features
Tape & Reel (TR) package
74LV series
14 pins
74LV74PW,118 Applications
There are a lot of Nexperia USA Inc. 74LV74PW,118 Flip Flops applications.
- Individual Asynchronous Resets
- ESCC
- EMI reduction circuitry
- Circuit Design
- Frequency Divider circuits
- Power down protection
- Shift Registers
- Data Synchronizers
- Clock pulse
- Data storage
