74LVC109D,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 2002 |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC109 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Load Capacitance | 50pF |
| Clock Frequency | 330MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.8ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 7.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Propagation Delay (tpd) | 7.5 ns |
| Length | 9.9mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
74LVC109D,112 Overview
The package is in the form of 16-SOIC (0.154, 3.90mm Width). Package Tubeembeds it. Currently, the output is configured to use Differential. Positive Edgeis the trigger it is configured with. Surface Mountmounts this electrical part. A voltage of 1.65V~3.6Vis used as the supply voltage. Currently, the operating temperature is -40°C~125°C TA. It belongs to the type JK Typeof flip flops. JK flip flop belongs to the 74LVCseries of FPGAs. In order for it to function properly, its output frequency should not exceed 330MHz. A total of 2elements are contained within it. As a result, it consumes 10μA of quiescent current without being affected by external factors. In 16terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. This D latch belongs to the family of 74LVC109. The power source is powered by 3.3V. A JK flip flop with a 5pFfarad input capacitance is used here. An electronic device belonging to the family LVC/LCX/Zcan be found here. There is a base part number FF/Latchesfor the RS flip flops. The maximal supply voltage (Vsup) reaches 3.6V. In order for the device to operate, it requires 3.3V power supplies.
74LVC109D,112 Features
Tube package
74LVC series
3.3V power supplies
74LVC109D,112 Applications
There are a lot of NXP USA Inc. 74LVC109D,112 Flip Flops applications.
- Divide a clock signal by 2 or 4
- ESD performance
- Dynamic threshold performance
- Functionally equivalent to the MC10/100EL29
- CMOS Process
- Buffer registers
- Balanced 24 mA output drivers
- Computing
- EMI reduction circuitry
- Data transfer
