74LVC16374ADGG-Q1J
| Parameters | |
|---|---|
| Turn On Delay Time | 7 ns |
| Family | LVC/LCX/Z |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 5.4ns @ 3.3V, 50pF |
| Screening Level | AEC-Q100 |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Clock Edge Trigger Type | Positive Edge |
| Width | 6.1mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 48-TFSOP (0.240, 6.10mm Width) |
| Number of Pins | 48 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2010 |
| Series | 74LVC |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 48 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Base Part Number | 74LVC16374 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Ports | 2 |
| Clock Frequency | 300MHz |
| Propagation Delay | 5.4 ns |
| Quiescent Current | 20μA |
74LVC16374ADGG-Q1J Overview
It is packaged in the way of 48-TFSOP (0.240, 6.10mm Width). There is an embedded version in the package Tape & Reel (TR). This output is configured with Tri-State, Non-Inverted. Positive Edgeis the trigger it is configured with. In this case, the electronic component is mounted in the way of Surface Mount. A 1.65V~3.6Vsupply voltage is required for it to operate. The operating temperature is -40°C~125°C TA. The type of this D latch is D-Type. In FPGA terms, D flip flop is a type of 74LVCseries FPGA. There should be no greater frequency than 300MHzon its output. A total of 2 elements are present. 48terminations have occurred. The 74LVC16374family includes it. The power supply voltage is 3.3V. This JK flip flop has a 5pFfarad input capacitance. It is a member of the LVC/LCX/Zfamily of D flip flop. It is mounted in the way of Surface Mount. 48pins are included in its design. In this device, the clock edge trigger type is Positive Edge. As soon as 3.6Vis reached, Vsup reaches its maximum value. A D flip flop with 2embedded ports is available. It consumes 20μA current.
74LVC16374ADGG-Q1J Features
Tape & Reel (TR) package
74LVC series
48 pins
74LVC16374ADGG-Q1J Applications
There are a lot of Nexperia USA Inc. 74LVC16374ADGG-Q1J Flip Flops applications.
- High Performance Logic for test systems
- Storage registers
- Latch-up performance
- Buffer registers
- Control circuits
- Bounce elimination switch
- Set-reset capability
- Event Detectors
- Frequency Divider circuits
- Data Synchronizers
