74LVC1G175GN,132
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2011 |
| Series | 74LVC |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 1.65V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.3mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVC1G175 |
| Function | Reset |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Number of Bits | 1 |
| Clock Frequency | 200MHz |
| Propagation Delay | 17 ns |
| Turn On Delay Time | 2.2 ns |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 40μA |
| Current - Output High, Low | 32mA 32mA |
| Output Polarity | TRUE |
| Max Propagation Delay @ V, Max CL | 4ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 2.5pF |
| fmax-Min | 200 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.35mm |
| Width | 0.9mm |
| RoHS Status | ROHS3 Compliant |
74LVC1G175GN,132 Overview
6-XFDFNis the packaging method. There is an embedded version in the package Tape & Reel (TR). In the configuration, Non-Invertedis used as the output. It is configured with the trigger Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A 1.65V~5.5Vsupply voltage is required for it to operate. A temperature of -40°C~125°C TAis used in the operation. This D latch has the type D-Type. It is a type of FPGA belonging to the 74LVC series. This D flip flop should not have a frequency greater than 200MHz. In total, it contains 1 elements. It consumes 40μA of quiescent 6terminations have occurred. If you search by 74LVC1G175, you will find similar parts. Power is provided by a 1.8V supply. The input capacitance of this JK flip flopis 2.5pF farads. LVC/LCX/Zis the family of this D flip flop. It is mounted by the way of Surface Mount. 6pins are included in its design. The clock edge trigger type for this device is Positive Edge. This flip flop is designed with 1 Bits. It reaches the maximum supply voltage (Vsup) at 5.5V.
74LVC1G175GN,132 Features
Tape & Reel (TR) package
74LVC series
6 pins
1 Bits
74LVC1G175GN,132 Applications
There are a lot of Nexperia USA Inc. 74LVC1G175GN,132 Flip Flops applications.
- Convert a momentary switch to a toggle switch
- Set-reset capability
- Automotive
- Memory
- Buffered Clock
- Balanced Propagation Delays
- Storage Registers
- Matched Rise and Fall
- Control circuits
- ESD performance
