74LVC1G175GV,125
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | SC-74, SOT-457 |
| Surface Mount | YES |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2011 |
| Series | 74LVC |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 1.65V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.95mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC1G175 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Output Current | 50mA |
| Number of Bits | 1 |
| Clock Frequency | 200MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 40μA |
| Current - Output High, Low | 32mA 32mA |
| Output Polarity | TRUE |
| Max Propagation Delay @ V, Max CL | 4ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 2.5pF |
| fmax-Min | 200 MHz |
| Length | 2.9mm |
| RoHS Status | ROHS3 Compliant |
74LVC1G175GV,125 Overview
The flip flop is packaged in SC-74, SOT-457. There is an embedded version in the package Tape & Reel (TR). The output it is configured with uses Non-Inverted. It is configured with a trigger that uses Positive Edge. This electronic part is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 1.65V~5.5V volts. In this case, the operating temperature is -40°C~125°C TA. Logic flip flops of this type are classified as D-Type. This type of FPGA is a part of the 74LVC series. There should be no greater frequency than 200MHzon its output. In total, there are 1 elements. There is 40μA quiescent consumption. In 6terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74LVC1G175 family contains this object. Power is provided by a 2.7V supply. The input capacitance of this T flip flop is 2.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. An electronic device belonging to the family LVC/LCX/Zcan be found here. A total of 6pins are provided on this board. There are 1bits in this flip flop. It reaches 5.5Vwhen the supply voltage is maximal (Vsup). In addition to its maximum design flexibility, the output current of the T flip flop is 50mA.
74LVC1G175GV,125 Features
Tape & Reel (TR) package
74LVC series
6 pins
1 Bits
74LVC1G175GV,125 Applications
There are a lot of Nexperia USA Inc. 74LVC1G175GV,125 Flip Flops applications.
- Clock pulse
- Single Down Count-Control Line
- ESD performance
- Frequency Divider circuits
- Communications
- Memory
- Test & Measurement
- 2 – Bit synchronous counter
- Consumer
- Shift registers
