74LVC1G175GW,125
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-TSSOP, SC-88, SOT-363 |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2005 |
| Series | 74LVC |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 1.65V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC1G175 |
| Function | Reset |
| Output Type | Non-Inverted |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Number of Circuits | 1 |
| Output Current | 50mA |
| Number of Bits | 1 |
| Clock Frequency | 200MHz |
| Propagation Delay | 17 ns |
| Quiescent Current | 100nA |
| Turn On Delay Time | 2.2 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 40μA |
| Current - Output High, Low | 32mA 32mA |
| Max Propagation Delay @ V, Max CL | 4ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 2.5pF |
| fmax-Min | 200 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Length | 2mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74LVC1G175GW,125 Overview
The flip flop is packaged in a case of 6-TSSOP, SC-88, SOT-363. D flip flop is embedded in the Tape & Reel (TR) package. Currently, the output is configured to use Non-Inverted. It is configured with the trigger Positive Edge. Surface Mountmounts this electrical part. A 1.65V~5.5Vsupply voltage is required for it to operate. A temperature of -40°C~125°C TAis used in the operation. It is an electronic flip flop with the type D-Type. JK flip flop belongs to the 74LVCseries of FPGAs. You should not exceed 200MHzin the output frequency of the device. There is a consumption of 40μAof quiescent energy. In 6terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. D latch belongs to the 74LVC1G175 family. An input voltage of 1.8Vpowers the D latch. Input capacitance of this device is 2.5pF farads. The electronic device belongs to the LVC/LCX/Zfamily. There is an electronic part that is mounted in the way of Surface Mount. As you can see from the design, it has pins with 6. This device has the clock edge trigger type of Positive Edge. The design is based on 1bits. 5.5Vis the maximum supply voltage (Vsup). 1 circuits are used to achieve its superior flexibility. With an output current of 50mA, it is possible to design the device in any way you want. In terms of quiescent current, it consumes 100nA .
74LVC1G175GW,125 Features
Tape & Reel (TR) package
74LVC series
6 pins
1 Bits
74LVC1G175GW,125 Applications
There are a lot of Nexperia USA Inc. 74LVC1G175GW,125 Flip Flops applications.
- Latch-up performance
- High Performance Logic for test systems
- Dynamic threshold performance
- Frequency Divider circuits
- ESCC
- Storage Registers
- Modulo – n – counter
- QML qualified product
- ESD protection
- Shift registers
