74LVC1G80GW,125
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 5-TSSOP, SC-70-5, SOT-353 |
| Number of Pins | 5 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2010 |
| Series | 74LVC |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 5 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 1.65V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC1G80 |
| Function | Standard |
| Output Type | Inverted |
| Polarity | Inverting |
| Number of Circuits | 1 |
| Output Current | 50mA |
| Number of Bits | 1 |
| Clock Frequency | 400MHz |
| Propagation Delay | 13 ns |
| Quiescent Current | 100nA |
| Turn On Delay Time | 1.8 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 200μA |
| Current - Output High, Low | 32mA 32mA |
| Max Propagation Delay @ V, Max CL | 4.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| fmax-Min | 200 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74LVC1G80GW,125 Overview
The flip flop is packaged in a case of 5-TSSOP, SC-70-5, SOT-353. The package Tape & Reel (TR)contains it. T flip flop uses Invertedas its output configuration. JK flip flop uses Positive Edgeas the trigger. There is an electronic component mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 1.65V~5.5V volts. A temperature of -40°C~125°C TAis considered to be the operating temperature. This D latch has the type D-Type. In FPGA terms, D flip flop is a type of 74LVCseries FPGA. You should not exceed 400MHzin the output frequency of the device. There is 200μA quiescent consumption. There have been 5 terminations. It is a member of the 74LVC1G80 family. It is powered by a voltage of 1.8V . JK flip flop input capacitance is 5pF farads. It is a member of the LVC/LCX/Zfamily of D flip flop. There is an electronic part that is mounted in the way of Surface Mount. 5pins are included in its design. This device has the clock edge trigger type of Positive Edge. It is designed with 1bits. Its superior flexibility is attributed to its use of 1 circuits. Featuring the maximum design flexibility, it has an output current of 50mA . Quiescent current is consumed by the D latch in the amount of 100nA.
74LVC1G80GW,125 Features
Tape & Reel (TR) package
74LVC series
5 pins
1 Bits
74LVC1G80GW,125 Applications
There are a lot of Nexperia USA Inc. 74LVC1G80GW,125 Flip Flops applications.
- Reduced system switching noise
- Frequency Divider circuits
- Test & Measurement
- High Performance Logic for test systems
- ESCC
- Data transfer
- Consumer
- ATE
- Power down protection
- Clock pulse
