74LVC273D,118
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2006 |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC273 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Clock Frequency | 230MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 8.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Propagation Delay (tpd) | 22.2 ns |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
74LVC273D,118 Overview
20-SOIC (0.295, 7.50mm Width)is the way it is packaged. As part of the package Tape & Reel (TR), it is embedded. In the configuration, Non-Invertedis used as the output. In the configuration of the trigger, Positive Edgeis used. There is an electrical part that is mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 1.65V~3.6V. It is operating at -40°C~125°C TA. A flip flop of this type is classified as a D-Type. In terms of FPGAs, it belongs to the 74LVC series. You should not exceed 230MHzin its output frequency. There are 1 elements in it. There is 10μA quiescent consumption. There are 20 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. This D latch belongs to the family of 74LVC273. The power supply voltage is 1.8V. Its input capacitance is 5pF farads. In terms of electronic devices, this device belongs to the LVC/LCX/Zfamily of devices. Vsup reaches 3.6V, the maximal supply voltage.
74LVC273D,118 Features
Tape & Reel (TR) package
74LVC series
74LVC273D,118 Applications
There are a lot of Nexperia USA Inc. 74LVC273D,118 Flip Flops applications.
- EMI reduction circuitry
- Pattern generators
- Control circuits
- Latch-up performance
- Single Down Count-Control Line
- Buffer registers
- Registers
- Cold spare funcion
- Test & Measurement
- Reduced system switching noise
