74LVC273DB,118
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 20-SSOP (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2006 |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Not For New Designs |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC273 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Clock Frequency | 230MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 8.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Propagation Delay (tpd) | 22.2 ns |
| Height Seated (Max) | 2mm |
| Length | 7.2mm |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LVC273DB,118 Overview
It is packaged in the way of 20-SSOP (0.209, 5.30mm Width). As part of the package Tape & Reel (TR), it is embedded. It is configured with Non-Invertedas an output. It is configured with a trigger that uses Positive Edge. There is an electric part mounted in the way of Surface Mount. A 1.65V~3.6Vsupply voltage is required for it to operate. The operating temperature is -40°C~125°C TA. D-Typeis the type of this D latch. FPGAs belonging to the 74LVCseries contain this type of chip. It should not exceed 230MHzin its output frequency. The list contains 1 elements. There is a consumption of 10μAof quiescent energy. A total of 20 terminations have been made. The 74LVC273 family contains it. A voltage of 1.8V is used as the power supply for this D latch. There is 5pF input capacitance for this T flip flop. It belongs to the family of electronic devices known as LVC/LCX/Z. The maximal supply voltage (Vsup) reaches 3.6V.
74LVC273DB,118 Features
Tape & Reel (TR) package
74LVC series
74LVC273DB,118 Applications
There are a lot of Nexperia USA Inc. 74LVC273DB,118 Flip Flops applications.
- 2 – Bit synchronous counter
- Load Control
- Event Detectors
- Asynchronous counter
- Functionally equivalent to the MC10/100EL29
- ESD protection
- ESCC
- Data transfer
- Individual Asynchronous Resets
- Data storage
