74LVC2G74DC-Q100H
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-VFSOP (0.091, 2.30mm Width) |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 1.65V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVC2G74 |
| JESD-30 Code | R-PDSO-G8 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Load Capacitance | 50pF |
| Number of Bits | 1 |
| Clock Frequency | 200MHz |
| Quiescent Current | 40μA |
| Family | LVC/LCX/Z |
| Current - Output High, Low | 32mA 32mA |
| Max Propagation Delay @ V, Max CL | 4.1ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Power Supply Current-Max (ICC) | 0.004mA |
| fmax-Min | 200 MHz |
| Length | 2.3mm |
| Width | 2mm |
| RoHS Status | ROHS3 Compliant |
74LVC2G74DC-Q100H Overview
The flip flop is packaged in a case of 8-VFSOP (0.091, 2.30mm Width). As part of the package Tape & Reel (TR), it is embedded. T flip flop is configured with an output of Differential. It is configured with a trigger that uses Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 1.65V~5.5V. -40°C~125°C TAis the operating temperature. It belongs to the type D-Typeof flip flops. This type of FPGA is a part of the 74LVC series. It should not exceed 200MHzin its output frequency. In total, it contains 1 elements. Currently, there are 8 terminations. The 74LVC2G74 family contains it. The D flip flop is powered by a voltage of 1.8V . JK flip flop input capacitance is 4pF farads. A device of this type belongs to the family of LVC/LCX/Z. This electronic part is mounted in the way of Surface Mount. It is designed with a number of bits of 1. There is a 5.5Vmaximum supply voltage (Vsup). In terms of quiescent current, it consumes 40μA .
74LVC2G74DC-Q100H Features
Tape & Reel (TR) package
74LVC series
1 Bits
74LVC2G74DC-Q100H Applications
There are a lot of Nexperia USA Inc. 74LVC2G74DC-Q100H Flip Flops applications.
- Parallel data storage
- Guaranteed simultaneous switching noise level
- Test & Measurement
- Storage registers
- Single Down Count-Control Line
- Frequency Divider circuits
- Buffer registers
- Instrumentation
- Consumer
- Shift Registers
