74LVC377D,112
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Number of Pins | 20 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Additional Feature | WITH HOLD MODE |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC377 |
| Function | Standard |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Bits | 8 |
| Clock Frequency | 330MHz |
| Propagation Delay | 6 ns |
| Quiescent Current | 100nA |
| Turn On Delay Time | 1.5 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Max Propagation Delay @ V, Max CL | 7.6ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Input Lines | 8 |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74LVC377D,112 Overview
The flip flop is packaged in 20-SOIC (0.295, 7.50mm Width). It is contained within the Tubepackage. Non-Invertedis the output configured for it. JK flip flop uses Positive Edgeas the trigger. It is mounted in the way of Surface Mount. Powered by a 1.65V~3.6Vvolt supply, it operates as follows. A temperature of -40°C~125°C TAis considered to be the operating temperature. It belongs to the type D-Typeof flip flops. It belongs to the 74LVCseries of FPGAs. Its output frequency should not exceed 330MHz. In total, there are 1 elements. As a result, it consumes 10μA of quiescent current without being affected by external factors. There are 20 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. D latch belongs to the 74LVC377 family. It is powered by a voltage of 2.7V . A 5pFfarad input capacitance is provided by this T flip flop. It is a member of the LVC/LCX/Zfamily of D flip flop. In this case, the electronic component is mounted in the way of Surface Mount. 20pins are included in its design. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. Flip flops designed with 8bits are used in this part. Vsup reaches its maximum value at 3.6V. Currently, there are 8 lines of input. As a result, it consumes 100nA of quiescent current without being affected by external factors. WITH HOLD MODEis also one of its characteristics.
74LVC377D,112 Features
Tube package
74LVC series
20 pins
8 Bits
74LVC377D,112 Applications
There are a lot of Nexperia USA Inc. 74LVC377D,112 Flip Flops applications.
- Count Modes
- Computers
- 2 – Bit synchronous counter
- Storage Registers
- Data storage
- Pattern generators
- Synchronous counter
- EMI reduction circuitry
- Convert a momentary switch to a toggle switch
- Clock pulse
