74LVC574APW,118
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 20 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.65mm |
| Base Part Number | 74LVC574 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Number of Ports | 2 |
| Output Current | 32mA |
| Number of Bits | 8 |
| Clock Frequency | 200MHz |
| Propagation Delay | 3.2 ns |
| Turn On Delay Time | 9 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Number of Inputs | 3 |
| Current - Output High, Low | 24mA 24mA |
| Max Propagation Delay @ V, Max CL | 7ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Input Lines | 8 |
| Clock Edge Trigger Type | Positive Edge |
| Length | 6.5mm |
| Width | 4.4mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74LVC574APW,118 Overview
The item is packaged in 20-TSSOP (0.173, 4.40mm Width)cases. D flip flop is included in the Tape & Reel (TR)package. There is a Tri-State, Non-Invertedoutput configured with it. It is configured with a trigger that uses a value of Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A supply voltage of 1.65V~3.6V is required for operation. A temperature of -40°C~125°C TAis considered to be the operating temperature. The type of this D latch is D-Type. The 74LVCseries comprises this type of FPGA. You should not exceed 200MHzin the output frequency of the device. D latch consists of 1 elements. As a result, it consumes 10μA of quiescent current without being affected by external factors. A total of 20 terminations have been made. D latch belongs to the 74LVC574 family. Power is provided by a 2.7V supply. A JK flip flop with a 5pFfarad input capacitance is used here. The electronic device belongs to the LVC/LCX/Zfamily. In this case, the electronic component is mounted in the way of Surface Mount. The 20pins are designed into the board. Its clock edge trigger type is Positive Edge. It is designed with a number of bits of 8. The flip flop has 2embedded ports. In addition to its maximum design flexibility, the output current of the T flip flop is 32mA. It has 8lines. 3 inputs are employed.
74LVC574APW,118 Features
Tape & Reel (TR) package
74LVC series
20 pins
8 Bits
74LVC574APW,118 Applications
There are a lot of Nexperia USA Inc. 74LVC574APW,118 Flip Flops applications.
- 2 – Bit synchronous counter
- Safety Clamp
- Automotive
- CMOS Process
- Single Up Count-Control Line
- Cold spare funcion
- Storage registers
- Data transfer
- Frequency Dividers
- Patented noise
