74LVC74APW,118
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 14-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Number of Pins | 14 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 1.2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC74 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Output Current | 50mA |
| Clock Frequency | 250MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 7.5 ns |
| Length | 5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74LVC74APW,118 Overview
As a result, it is packaged as 14-TSSOP (0.173, 4.40mm Width). You can find it in the Tape & Reel (TR)package. T flip flop is configured with an output of Differential. It is configured with a trigger that uses a value of Positive Edge. Surface Mountis occupied by this electronic component. A 1.2V~3.6Vsupply voltage is required for it to operate. In this case, the operating temperature is -40°C~125°C TA. D-Typedescribes this flip flop. JK flip flop belongs to the 74LVCseries of FPGAs. In order for it to function properly, its output frequency should not exceed 250MHz. In total, there are 2 elements. As a result, it consumes 10μA of quiescent current without being affected by external factors. 14terminations have occurred. It is a member of the 74LVC74 family. The D flip flop is powered by a voltage of 2.7V . The input capacitance of this T flip flop is 4pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. Electronic devices of this type belong to the LVC/LCX/Zfamily. There are 14pins on it. Vsup reaches its maximum value at 3.6V. It offers maximum design flexibility with its output current of 50mA.
74LVC74APW,118 Features
Tape & Reel (TR) package
74LVC series
14 pins
74LVC74APW,118 Applications
There are a lot of Nexperia USA Inc. 74LVC74APW,118 Flip Flops applications.
- Bus hold
- Supports Live Insertion
- Modulo – n – counter
- Balanced 24 mA output drivers
- Divide a clock signal by 2 or 4
- Parallel data storage
- Bounce elimination switch
- High Performance Logic for test systems
- Communications
- Safety Clamp
