74LVC823ABQ,115
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 24-VFQFN Exposed Pad |
| Number of Pins | 24 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | QUAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC823 |
| Function | Master Reset |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Ports | 2 |
| Clock Frequency | 200MHz |
| Propagation Delay | 11.5 ns |
| Turn On Delay Time | 3.7 ns |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 9 |
| Max Propagation Delay @ V, Max CL | 10ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Clock Edge Trigger Type | Positive Edge |
| Length | 5.5mm |
| Width | 3.5mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
74LVC823ABQ,115 Overview
24-VFQFN Exposed Padis the way it is packaged. D flip flop is embedded in the Tape & Reel (TR) package. T flip flop is configured with an output of Tri-State, Non-Inverted. Positive Edgeis the trigger it is configured with. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates with an input voltage of 1.65V~3.6V volts. A temperature of -40°C~125°C TAis used in the operation. This D latch has the type D-Type. JK flip flop belongs to the 74LVCseries of FPGAs. It should not exceed 200MHzin its output frequency. In total, it contains 1 elements. T flip flop consumes 10μA quiescent energy. The number of terminations is 24. JK flip flop belongs to 74LVC823 family. A voltage of 2.7V is used to power it. JK flip flop input capacitance is 5pF farads. This D flip flop belongs to the family of LVC/LCX/Z. There is an electronic component mounted in the way of Surface Mount. With its 24pins, it is designed to work with most electronic flip flops. A Positive Edgeclock edge trigger is used in this device. Vsup reaches its maximum value at 3.6V. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.
74LVC823ABQ,115 Features
Tape & Reel (TR) package
74LVC series
24 pins
74LVC823ABQ,115 Applications
There are a lot of Nexperia USA Inc. 74LVC823ABQ,115 Flip Flops applications.
- Instrumentation
- Test & Measurement
- Guaranteed simultaneous switching noise level
- Storage registers
- Automotive
- Convert a momentary switch to a toggle switch
- Load Control
- Consumer
- Buffered Clock
- EMI reduction circuitry
