74LVC823APW,112
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 24-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 24 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Additional Feature | WITH CLEAR AND CLOCK ENABLE |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.65mm |
| Base Part Number | 74LVC823 |
| Function | Master Reset |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Ports | 2 |
| Number of Bits | 9 |
| Clock Frequency | 200MHz |
| Propagation Delay | 5.1 ns |
| Turn On Delay Time | 3.7 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Max Propagation Delay @ V, Max CL | 10ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Input Lines | 9 |
| Clock Edge Trigger Type | Positive Edge |
| Length | 7.8mm |
| Width | 4.4mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
74LVC823APW,112 Overview
It is embeded in 24-TSSOP (0.173, 4.40mm Width) case. D flip flop is included in the Tubepackage. In the configuration, Tri-State, Non-Invertedis used as the output. There is a trigger configured with Positive Edge. It is mounted in the way of Surface Mount. The JK flip flop operates at 1.65V~3.6Vvolts. A temperature of -40°C~125°C TAis used in the operation. D-Typeis the type of this D latch. FPGAs belonging to the 74LVCseries contain this type of chip. It should not exceed 200MHzin terms of its output frequency. A total of 1elements are contained within it. As a result, it consumes 10μA quiescent current. The number of terminations is 24. It is a member of the 74LVC823 family. A voltage of 1.8V is used as the power supply for this D latch. There is 5pF input capacitance for this T flip flop. In this case, the D flip flop belongs to the LVC/LCX/Zfamily. It is mounted in the way of Surface Mount. 24pins are included in its design. It has a clock edge trigger type of Positive Edge. There are 9bits in its design. Vsup reaches its maximum value at 3.6V. This D flip flop is equipped with 0 ports. Currently, there are 9 input lines present. Additionally, you may refer to the additional WITH CLEAR AND CLOCK ENABLE of the electronic flip flop.
74LVC823APW,112 Features
Tube package
74LVC series
24 pins
9 Bits
74LVC823APW,112 Applications
There are a lot of Nexperia USA Inc. 74LVC823APW,112 Flip Flops applications.
- Counters
- Digital electronics systems
- Asynchronous counter
- Communications
- Clock pulse
- Individual Asynchronous Resets
- Memory
- Storage Registers
- Registers
- Safety Clamp
