74LVCH16374ABX,518
| Parameters | |
|---|---|
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 5.4ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 100000000Hz |
| Height Seated (Max) | 0.5mm |
| Length | 6mm |
| Width | 4mm |
| RoHS Status | RoHS Compliant |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 60-XFQFN Dual Rows, Exposed Pad |
| Number of Pins | 60 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVCH |
| JESD-609 Code | e3 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 2 (1 Year) |
| Number of Terminations | 60 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | BOTTOM |
| Terminal Form | BUTT |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVCH16374 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1.65V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Number of Bits | 16 |
| Clock Frequency | 300MHz |
| Propagation Delay | 7.5 ns |
| Quiescent Current | 100nA |
| Turn On Delay Time | 7 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 20μA |
74LVCH16374ABX,518 Overview
It is packaged in the way of 60-XFQFN Dual Rows, Exposed Pad. It is included in the package Tape & Reel (TR). This output is configured with Tri-State, Non-Inverted. The trigger it is configured with uses Positive Edge. There is an electric part mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 1.65V~3.6V volts. It is operating at -40°C~125°C TA. A flip flop of this type is classified as a D-Type. It is a type of FPGA belonging to the 74LVCH series. Its output frequency should not exceed 300MHz Hz. In total, it contains 2 elements. T flip flop consumes 20μA quiescent energy. There are 60 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The 74LVCH16374family includes it. It is powered from a supply voltage of 3.3V. There is 5pF input capacitance for this T flip flop. Devices in the LVC/LCX/Zfamily are electronic devices. This electronic part is mounted in the way of Surface Mount. This board is designed with 60pins on it. The clock edge trigger type for this device is Positive Edge. The RS flip flops belongs to FF/Latches base part number. The flip flop is designed with 16bits. The maximal supply voltage (Vsup) reaches 3.6V. Normally, the supply voltage (Vsup) should be kept above 1.65V. This D flip flop is well suited for TAPE AND REEL based on its reliable performance. In order for the device to operate, it requires 3.3V power supplies. The flip flop has 2embedded ports. Quiescent current is consumed by the D latch in the amount of 100nA.
74LVCH16374ABX,518 Features
Tape & Reel (TR) package
74LVCH series
60 pins
16 Bits
3.3V power supplies
74LVCH16374ABX,518 Applications
There are a lot of Nexperia USA Inc. 74LVCH16374ABX,518 Flip Flops applications.
- Common Clocks
- Single Down Count-Control Line
- Event Detectors
- Automotive
- Counters
- Digital electronics systems
- Memory
- Consumer
- Functionally equivalent to the MC10/100EL29
- Differential Individual
