74LVCH16374ADGG:11
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 48-TFSOP (0.240, 6.10mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LVCH |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 48 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVCH16374 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 1.65V |
| Number of Ports | 2 |
| Clock Frequency | 300MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 20μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 5.4ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Propagation Delay (tpd) | 15.6 ns |
| Width | 6.1mm |
| RoHS Status | ROHS3 Compliant |
74LVCH16374ADGG:11 Overview
It is packaged in the way of 48-TFSOP (0.240, 6.10mm Width). D flip flop is included in the Tubepackage. In the configuration, Tri-State, Non-Invertedis used as the output. Positive Edgeis the trigger it is configured with. In this case, the electronic component is mounted in the way of Surface Mount. Powered by a 1.65V~3.6Vvolt supply, it operates as follows. It is operating at -40°C~125°C TA. D-Typeis the type of this D latch. JK flip flop belongs to the 74LVCHseries of FPGAs. It should not exceed 300MHzin its output frequency. D latch consists of 2 elements. As a result, it consumes 20μA quiescent current. 48terminations have occurred. The object belongs to the 74LVCH16374 family. A voltage of 1.8V is used as the power supply for this D latch. This JK flip flop has a 5pFfarad input capacitance. It belongs to the family of electronic devices known as LVC/LCX/Z. Vsup reaches 3.6V, the maximal supply voltage. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 1.65V. The flip flop has 2embedded ports.
74LVCH16374ADGG:11 Features
Tube package
74LVCH series
74LVCH16374ADGG:11 Applications
There are a lot of Nexperia USA Inc. 74LVCH16374ADGG:11 Flip Flops applications.
- Common Clocks
- Synchronous counter
- Matched Rise and Fall
- Guaranteed simultaneous switching noise level
- Divide a clock signal by 2 or 4
- Storage registers
- Safety Clamp
- 2 – Bit synchronous counter
- Shift Registers
- Data storage
