74LVQ273SC
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVQ |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2V |
| Clock Frequency | 90MHz |
| Family | LVQ |
| Current - Quiescent (Iq) | 40μA |
| Current - Output High, Low | 12mA 12mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 8.5ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Propagation Delay (tpd) | 20.5 ns |
| fmax-Min | 75 MHz |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
74LVQ273SC Overview
The flip flop is packaged in 20-SOIC (0.295, 7.50mm Width). There is an embedded version in the package Tube. It is configured with Non-Invertedas an output. JK flip flop uses Positive Edgeas the trigger. The electronic part is mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 2V~3.6V. A temperature of -40°C~85°C TAis considered to be the operating temperature. Logic flip flops of this type are classified as D-Type. JK flip flop belongs to the 74LVQseries of FPGAs. This D flip flop should not have a frequency greater than 90MHz. In total, it contains 1 elements. T flip flop consumes 40μA quiescent energy. A total of 20 terminations have been made. Power is provided by a 2.7V supply. The input capacitance of this JK flip flopis 4.5pF farads. In this case, the D flip flop belongs to the LVQfamily. It reaches 3.6Vwhen the supply voltage is maximal (Vsup). Keeping the supply voltage (Vsup) above 2V is necessary for normal operation.
74LVQ273SC Features
Tube package
74LVQ series
74LVQ273SC Applications
There are a lot of Rochester Electronics, LLC 74LVQ273SC Flip Flops applications.
- Memory
- Latch
- Single Down Count-Control Line
- Matched Rise and Fall
- Registers
- Cold spare funcion
- Frequency Dividers
- Guaranteed simultaneous switching noise level
- Control circuits
- Bus hold
