74LVQ74MTR
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 14 |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVQ |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | CMOS |
| Voltage - Supply | 2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVQ74 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2V |
| Load Capacitance | 50pF |
| Number of Bits | 1 |
| Clock Frequency | 250MHz |
| Propagation Delay | 12 ns |
| Turn On Delay Time | 6.3 ns |
| Family | LVQ |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 2μA |
| Current - Output High, Low | 24mA 24mA |
| Max Propagation Delay @ V, Max CL | 9ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Number of Input Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Length | 8.65mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74LVQ74MTR Overview
The item is packaged in 14-SOIC (0.154, 3.90mm Width)cases. D flip flop is embedded in the Tape & Reel (TR) package. The output it is configured with uses Differential. JK flip flop uses Positive Edgeas the trigger. There is an electric part mounted in the way of Surface Mount. Powered by a 2V~3.6Vvolt supply, it operates as follows. The operating temperature is -55°C~125°C TA. D-Typeis the type of this D latch. JK flip flop is a part of the 74LVQseries of FPGAs. It should not exceed 250MHzin terms of its output frequency. D latch consists of 2 elements. Despite external influences, it consumes 2μAof quiescent current. A total of 14 terminations have been made. This D latch belongs to the family of 74LVQ74. The power supply voltage is 2.7V. This T flip flop has a capacitance of 4pF farads at the input. LVQis the family of this D flip flop. There is an electronic component mounted in the way of Surface Mount. It is designed with 14 pins. There is a clock edge trigger type of Positive Edgeon this device. The RS flip flops belongs to FF/Latches base part number. There are 1bits in its design. As soon as 3.6Vis reached, Vsup reaches its maximum value. It is imperative that the supply voltage (Vsup) is maintained above 2Vin order to ensure normal operation. A reliable performance of this D flip flop makes it well suited for use in TAPE AND REEL. The D latch runs on a voltage of 3.3V volts. The number of input lines is 1.
74LVQ74MTR Features
Tape & Reel (TR) package
74LVQ series
14 pins
1 Bits
3.3V power supplies
74LVQ74MTR Applications
There are a lot of STMicroelectronics 74LVQ74MTR Flip Flops applications.
- ESCC
- Modulo – n – counter
- Shift registers
- Differential Individual
- Data Synchronizers
- Safety Clamp
- Functionally equivalent to the MC10/100EL29
- Latch-up performance
- Circuit Design
- Data storage
